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Results 1 to 25 of 282

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Single-shot measurement of the Josephson charge qubitASTAFIEV, O; PASHKIN, Yu. A; YAMAMOTO, T et al.Physical review B. Condensed matter and materials physics. 2004, Vol 69, Num 18, pp 180507.1-180507.4, issn 1098-0121Article

A 4Gb/s/pin dual-reference simultaneous bidirectional I/O circuit for memory-bus interfaceKIM, Woo-Seop; CHOI, Jung-Hwan; KIM, Jin-Hyun et al.IEEE International Solid-State Circuits Conference. 2004, pp 412-413, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A method to eliminate the event accumulation problem from a memory affected by multiple bit upsetsMAESTRO, Juan Antonio; REVIRIEGO, Pedro.Microelectronics and reliability. 2009, Vol 49, Num 7, pp 707-715, issn 0026-2714, 9 p.Article

Vertebrates that never sleep : Implications for sleep's basic functionKAVANAU, J. L.Brain research bulletin. 1998, Vol 46, Num 4, pp 269-279, issn 0361-9230Article

Working memory networks and the origin of language areas in the human brainABOITIZ, F.Medical hypotheses. 1995, Vol 44, Num 6, pp 504-506, issn 0306-9877Article

Emerging Nanoscale Memory and Logic Devices : A Critical AssessmentHUTCHBY, Fames A; CAVIN, Ralph; ZBIRNOV, Victor et al.Computer (Long Beach, CA). 2008, Vol 41, Num 5, pp 28-32, issn 0018-9162, 5 p.Article

Protein-Based Disk Recording at Areal Densities beyond 10 Terabits/inKHIZROEV, S; IKKAWI, R; AMOS, N et al.MRS bulletin. 2008, Vol 33, Num 9, pp 864-871, issn 0883-7694, 8 p.Article

Prévoir l'avenir du paysage audiovisuel = Future forcast for audiovisualLAVEN, P. A.UER-revue technique. 1998, Num 276, pp 4-11, issn 1019-6595Article

Multiple-valued logic memory circuitCURRENT, K. W.International journal of electronics. 1995, Vol 78, Num 3, pp 547-555, issn 0020-7217Article

Self-initializing memory elementsBAPIRAJU VINNAKOTA; RAMESH HARJANI.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1995, Vol 42, Num 7, pp 461-472, issn 1057-7130Article

Circuit analysis of the memristive stateful implication gateXUDONG FANG; YUHUA TANG.Electronics letters. 2013, Vol 49, Num 20, pp 1282-1283, issn 0013-5194, 2 p.Article

Computing with Novel Floating-Gate Devices : NANOSCALE ARCHITECTURESSCHINKE, Daniel; DI SPIGNA, Neil; SHIVESHWARKAR, Mihir et al.Computer (Long Beach, CA). 2011, Vol 44, Num 2, pp 29-36, issn 0018-9162, 8 p.Article

On the dynamics of a single-bit stochastic-resonance memory deviceIBANEZ, S. A; FIERENS, P. I; PERAZZO, R. P. J et al.The European physical journal. B, Condensed matter physics (Print). 2010, Vol 76, Num 1, pp 49-55, issn 1434-6028, 7 p.Article

A silicon single-electron transistor memory operating at room temperatureGUO, L; LEOBANDUNG, E; CHOU, S. Y et al.Science (Washington, D.C.). 1997, Vol 275, Num 5300, pp 649-651, issn 0036-8075Article

Resistive circuit topologies that admit several solutionsFOSSEPREZ, M; HASLER, M.International journal of circuit theory and applications. 1990, Vol 18, Num 6, pp 625-638, issn 0098-9886Article

An interpolating sense circuit for molecular memoryNISHIDA, Yoshio; WENTAI LIU.Custom integrated circuits conference. 2002, pp 103-106, isbn 0-7803-7250-6, 4 p.Conference Paper

New clock-feedthrough compensation scheme for switched-current circuitsMIN, B.-M; KIM, S.-W.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1998, Vol 45, Num 11, pp 1508-1511, issn 1057-7130Article

March U : a test for unlinked memory faultsVAN DE GOOR, A. J; GAYDADJIEV, G. N.IEE proceedings. Circuits, devices and systems. 1997, Vol 144, Num 3, pp 155-160, issn 1350-2409Article

Is memristor a dynamic element?BAO, B. C; LIU, Z; LEUNG, H et al.Electronics letters. 2013, Vol 49, Num 24, pp 1523-1525, issn 0013-5194, 3 p.Article

Memory compaction and power optimization for wavelet-based codersFERENTINOS, V; MILIA, M; LAFRUIT, G et al.Lecture notes in computer science. 2003, pp 328-337, issn 0302-9743, isbn 3-540-20074-6, 10 p.Conference Paper

Etching new IC materials for memory devicesDEORNELLAS, S. P; COFER, A.Solid state technology. 1998, Vol 41, Num 8, pp 53-58, issn 0038-111X, 4 p.Article

Memory based architecture and its implementation scheme named bit-parallel block-parallel functional memory type parallel processor BPBP FMPPTAMARU, K; KOBAYASHI, K; ONODERA, H et al.Computers & electrical engineering. 1998, Vol 24, Num 1-2, pp 17-31, issn 0045-7906Article

New architectures for M4R shape codingSTROMING, J. W; KANG, Y; KANG, S. M et al.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1998, Vol 45, Num 5, pp 556-562, issn 1057-7130Article

A survey of behavioral modeling of ferroelectric capacitorsSHEIKHOLESLAMI, A; GLENN GULAK, P.IEEE transactions on ultrasonics, ferroelectrics, and frequency control. 1997, Vol 44, Num 4, pp 917-924, issn 0885-3010Article

On-chip memory module designs for video-signal processingCHANG, T.-S; JEN, C.-W.IEE proceedings. Circuits, devices and systems. 1997, Vol 144, Num 3, pp 138-144, issn 1350-2409Article

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